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OKI Semiconductor ML2302
Recording and Playback LSI with Built-in 2-Bit ADPCM2 Supported FIFO
FEDL2302DIGEST-05
Issue Date: Dec. 27, 2004
GENERAL DESCRIPTION
The ML2302 is a recording and playback LSI with built-in FIFO memories for buffering. It employs the new 2-bit ADPCM2 algorithm in addition to conventional 4-bit OKIADPCM and 4-bit OKIADPCM2 algorithms. The ML2302 operates at 2.7 to 3.6 V and supports a variety of applications.
FEATURES
* Built-in two 1024-bit FIFOs (buffering time of 32 ms when using 8 kHz sampling frequency and 4-bit ADPCM) * Supports five compression algorithms for recording and playback: 2-bit OKIADPCM2; 4/5/6/7-bit OKIADPCM2; 4-bit OKIADPCM; 8/16-bit straight PCM; 8-bit OKI Nonlinear PCM * Source oscillation frequency 16.384 MHz * Sampling frequency (fsam) 4.0 to 12.8 kHz (OKIADPCM2) 4.0 to 25.6 kHz (8-bit straight PCM) * Supports 8-bit bus interface. * Built-in voice level detection function (VAC) * Built-in noise injection function * Supports external DAC interface. * Built-in volume control circuit (0 dB to -44 dB: -2 dB step, -44 dB to -80 dB: -4 dB step) * Built-in 14-bit A/D converter and 14-bit D/A converter * Built-in low pass filter (LPF) (recording side: analog filter, playback side: digital filter) * Built-in speaker amplifier (100 mW, 8) * Power supply voltage : +2.7 to +3.6 V * Package : 64-pin plastic TQFP (TQFP64-P-1010-0.50-K) (ML2302TB) : 71-pin W - CSP
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BLOCK DIAGRAM
SPOUT- SPOUT+
MOUT
MIN LIN
SG
DAC
VR
LPF
LPF Volume Controller
x1
VR SPVDD CB1 CB2 SG VR SG TEST0 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 VCK SIOCK ADSD DASD AVDD AGND DVDD DGND
VOXO
LOUT
AOUT
FIFOST EMP MID FUL FIFO CH D7 to 0
ADC
Analyzer Serial Port Synthesizer DMA I/F Timing Controller DREQL DACKL IOW IOR XT XT RESET
BUSY CBUSY CS D/C WR RD
MCU I/F
SPIN
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PIN CONFIGURATION (TOP VIEW)
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
CS D/C BUSY SIOCK DASD ADSD VCK DGND DACKL DREQL IOW IOR VOXO XT XT TEST0
D0 D1 D2 D3 D4 D5 D6 D7 DVDD TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
RD WR DVDD FUL MID EMP CH CBUSY RESET FIFOST DGND VR CB1 CB2 SPVDD AVDD(SP)
AVDD SG LOUT LIN MOUT MIN AGND TEST9 AOUT SPIN SPOUT- SPOUT+ N.C. N.C. N.C. AGND (SP)
N.C.: No Connection 64-pin plastic TQFP
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N.C.
RD
FUL
CH
RESET
VR
CB2
N.C.
N.C.
9 8 7 6 5 4 3 2 1
N.C.
TEST0
DVDD
EMP
FIFOST CB1
SPVDD AVDD(SP) AGND(SP)
XT
XT
WR
MID
CBUSY
DGND
N.C.
N.C.
N.C.
IOR
VOXO
IOW
SPOUT+ SPOUT-
SPIN
DACKL DREQL DGND
AGND TEST9
AOUT
VCK
ADSD
DASD
LIN
MOUT
MIN
SIOCK
BUSY
D/C
D4
DVDD
TEST2
SG
LOUT
CS
D0
D1
D2
D6
TEST3 TEST5 TEST8
AVDD
N.C.
N.C.
D3
D5
D7
TEST4 TEST6 TEST7
N.C.
JHGFEDCBA
INDEX
71-pin W-CSP (Bottom View)
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PIN DESCRIPTIONS
Pin (WCSP) H2, G2, F2, G1, F3, F1, E2, E1 G7 H9 J2 G3 H3 E7 F8 F7 Pin (TQFP) 1 to 8 Symbol Type Description Bidirectional data bus. Command and data inputs from an external microcontroller and memory, and status and data outputs to an external microcontroller and memory. Write pulse input pin. This pin pulses "L" when command or voice data is input to D7 to D0 pins. Read pulse input pin. This pin pulses "L" when status or voice data is output to D7 to D0. Accepts write pulse and read pulse when this pin is "L". Voice data is input or output to and from D7 to D0 when this pin is "H". This pin outputs a "L" level during RECORDING, PLAYBACK, or PAUSE. Accepts a command during this pin is "H". "H" indicates that there is no data in FIFO memory. During playback, voice synthesis starts when EMP changes to "L". Active "H" can be changed to active "L". "H" level indicates that there is more than half of the FIFO memory. "H" level indicates that FIFO memory is full of data. During playback, this pin is "H" and data cannot be written in FIFO memory. During recording, data is not written after FIFO memory is full of data. Active "H" can be changed to active "L". This pin should be set at a "L" level normally and be set at a "H" level when DMA is used. When DMA transfer is selected, "H" level DREQL outputs a signal to request a DMA transfer. Active "H" can be changed to active "L". Input to DACKL a signal when DMA transfer is permitted by the DMA controller. when DACKL is "L", IOW and IOR signals are accepted. Active "L" can be changed to active "H" by command input. If DMA transfer is not used, set this pin to "H" level. Write pulse Input pin to write external memory data to ML2302 during DMA transfer. If DMA transfer is not used, set this pin to "H" level. Read pulse input pin to read data of ML2302 during DMA transfer. If DMA transfer is not used, set this pin to "H" level. 16-bit serial data input pin when external A/D converter is used. If external A/D converter is not used, set this pin to "L" level. 16-bit serial data input pin when external D/A converter is used.
D7 to 0
I/O
47 48 64 63 62 41 43 44
WR RD CS D/C BUSY CBUSY EMP MID
I I I I O O O O
G9
45
FUL
O
F9 H5
42 55
CH DREQL
I O
J5
56
DACKL
I
G6
54
IOW
I
J6 H4 G4
53 59 60
IOR ADSD DASD
I I O
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Pin (WCSP) J3 J4 J7 H7 E9 E8 B3 A4 C4 B4 A3 A5 H6 H8, B2 E3, G8 D7, G5 A2, B8 C5, A8 C9, D8 C8 D9 A6 B6 C6 D1, D2, D3, C1, C2, B1, B5
Pin (TQFP) 61 58 51 50 40 39 18 22 20 21 19 25 52 49, 16 9, 46 38, 57 17, 33 23, 32 36 35 34 37 26 27 28 10~15 ,24
Symbol SIOCK VCK XT XT RESET FIFOST SG MIN LIN MOUT LOUT AOUT VOXO TEST0, 8 DVDD DGND AVDD AGND CB1 CB2 SPVDD VR SPIN SPOUT- SPOUT+ TEST2 to 7, 9
Type I/O I/O I O I I O I O O O I -- -- -- -- O O O I O O
Description 16-bit serial data transfer clock when external A/D or D/A converter is used. Outputs sampling frequency selected. Input pin when slave mode is selected. Oscillator connection pins. when external clock is used, input clock into XT pin and leave XT pin open. Oscillation stops during reset or power down mode. Figure (a) shows Oscillation Equivalent Circuit. When this pin is "L", the LSI is initialized and AOUT is set to the GND level. When this pin is "L", EMP, MID, and FULL of playback FIFO can be monitored. When this pin is "H", EMP, MID, and FULL of record FIFO can be monitored. Analog circuit signal ground pin. This pin is connected to GND during reset or power down mode. Inverting input pin for built-in OP amplifier. Non-inverting input pin is connected to SG (Signal Ground). MOUT is the output of internal OP amplifier to MIN, and LOUT is to LIN. This is the output of the analog playback waveform. Voice level detection signal Pins for testing. Set the pins to "L". Digital power supply pin. Insert a minimum 0.1 F bypass capacitor between this pin and DGND pin Digital GND pin. Analog power supply pin. Insert a minimum 0.1 F bypass capacitor between this pin and AGND pin. Analog GND pin. This pin is used to connect a capacitor for voltage multiplier power supply. Insert a 1 F capacitor between CB1 and CB2. Voltage multiplier power supply output pin for speaker amplifier. Connect a 1 F capacitor to this pin in order to stabilize the speaker amplifier circuit. Bias output pin for speaker amplifier. Set this pin to the GND level during reset or power down mode. Voice signal input pin for speaker amplifier. Speaker amplifier output pin. This pin outputs a signal in reverse phase to the signal that is input to the SPIN pin. Speaker amplifier output pin. This pin outputs a signal in phase to the signal that is input to the SPIN pin. Pins for testing. Leave these pins open.
O
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RESET XT XT
power down Internal OSC
Figure (a) Oscillation Equivalent Circuit
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ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Maximum Power Dissipation Temperature Storage Symbol VDD VIN PD TSTG Condition Ta = 25C -- Rating -0.3 to +7.0 -0.3 to VDD +0.3 689.6 -55 to +150 Unit V V mW C
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Operating Temperature Master Clock Frequency Speaker Amplifier Load Impedance Symbol VDD TOp fOSC RLSP Condition DGND = AGND = 0 V -- -- -- Rating +2.7 to +3.6 -10 to +70 16.384 8 to Unit V C MHz
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ELECTRICAL CHARACTERISTICS
DC Characteristics
(DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -10 to +70C) Condition Min. Typ. Max. Unit -- -- 0.85 x VDD -- VDD - 0.3 IOH = -40 A VOH2 VOL1 IOL = 2 mA VOL2 IIH1 VIH = VDD IIH2 IIL1 VIL = GND IIL2 IDD fosc = 16 MHz, without load At reset, without load Ta = -10 to +50C At reset, without load Ta = +50 to +70C -7 -- -- -- -- 15 -- -- -1 20 10 50 A mA A A 1 -10 -- -- 7 -- A A -- -- -- -- 0.8 10 V A VDD - 0.3 -- -- -- -- 0.45 V V -- -- -- -- 0.15 x VDD -- V V V
Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage (*1, *5) High-level Output Voltage (*2, *5) Low-level Output Voltage (*1, *5) Low-level Output Voltage (*2, *5) High-level Input Current (*3) High-level Input Current (*4) Low-level Input Current (*3) Low-level Input Current (*4) Operating Current Consumption Standby Current Consumption
Symbol VIH VIL VOH1
IDDS
*1 : Applied to input pins excluding XT pin. *2 : Applied to XT pin. *3 : Applied to output pins excluding XT pin. *4 : Applied to XT pin. *5 : If an output pin is shortcircuited to VDD or GND, the LSI may be damaged.
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Analog Characteristics
(DVDD = AVDD = 2.7 to 3.6 V, DGND = AGND = 0 V, Ta = -10 to +70C) Condition Min. Typ. Max. Unit Without load VDD = 3 V fin = 0 to 4 kHz DAC output is selected AOUT = 1/2VDD (Excluding MIC amplifier) MIC amplifier -- -- -- VDD = 3.0 V SPIN SPOUT- (Loop resistor is not connected) fIN = 10 kHz SPOUT- SPOUT+ VDD = 3.0 V RL = 8 THD 10% No signal is input. No signal is input. IOH = +10 mA IOL = -10 mA -- 0.75 40 30 1 8.1 50 50 1.22 1.47 1 40 -0.4 100 -- -- -- 50 -- 11.6 -- -- 1.25 1.5 -- -- 0 -- 40 2.25 -- 70 -- 15.1 -- -- 1.28 1.53 -- -- 0.4 -- mV V dB k M k k k V V M dB dB mW
Parameter D/A Output Relative Error LOUT Allowable Voltage Range OP Amplifier Open Loop Gain DAC Output Impedance OP Amplifier Input Impedance MIC Amplifier Input Impedance MOUT, LOUT Load Resistance AOUT Load Resistance VR Output Voltage SG Output Voltage SPIN Input Impedance Voltage Gain
Symbol |VDAE| VLOUT GOP RDAO RINA RINAM ROUTA RAOL VVR VSG RISP AV1 AV2
Differential Output Power SPOUT+/- Output Voltage SPOUT+/- Output Offset Voltage SPOUT+/- Output "H" Voltage SPOUT+/- Output "L" Voltage
PD1
VSP VSPOF VSPH VSPL
1.17 -- 2.2 --
1.25 -- -- --
1.33 50 -- 0.25
V mV V V
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FUNCTIONAL DESCRIPTION
Voice Synthesis Algorithms The ML2302 supports five PCM algorithms to process various kinds of voices. 1. 2. 3. 4. 5. 4-bit OKIADPCM algorithm 4/5/6/7/8-bit OKIADPCM2 algorithm 2-bit OKIADPCM algorithm 8/16-bit straight PCM algorithm 8-bit OKI Non-linear PCM algorithm
Voice Synthesis Algorithms and Sampling Frequencies during Recording and Playback The relationships between the voice synthesis algorithms and sampling frequencies available during recording and playback are shown in Tables 1.1.1 and 1.1.2. Table 1.1.1 During Recording
fsam (kHz) Voice synthesis algorithm 4-bitADPCM 4/5/6/7/8-bitADPCM2 2-bitADPCM2 8-bit straight PCM 16-bit straight PCM 8-bit Non-linear PCM
4.0
5.3
6.1
6.4
8.0
9.8
10.7
11.6
12.8
14.2
16.0
18.3
21.3
25.6
x
x
x
x
x
x
x
x
xxxxx xxxxx xxxxx x x xx x x x x
Table 1.1.2 During Playback
fsam (kHz) Voice synthesis algorithm 4-bitADPCM 4/5/6/7/8-bitADPCM2 2-bitADPCM 8-bit straight PCM 16-bit straight PCM 8-bit Non-linear PCM
4.0
5.3
6.1
6.4
8.0
9.8
10.7
11.6
12.8
14.2
16.0
18.3
21.3
25.6

xxxxx xxxxx xxxxx xx xx
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Data Configuration The data configuration of each voice synthesis algorithm is shown in Tables 1.2.1 to 1.2.7. Table 1.2.1 2-bitADPCM2 Algorithm
D7 MSB1 D6 LSB1 D5 MSB2 D4 LSB2 D3 MSB3 D2 LSB3 D1 MSB4 D0 LSB4
Table 1.2.2 4-bitADPCM Algorithm, 4-bit ADPCM2 Algorithm
D7 MSB1 D6 3SB1 D5 2SB1 D4 LSB1 D3 MSB2 D2 3SB2 D1 2SB2 D0 LSB2
Table 1.2.3 5-bitADPCM2 Algorithm
D7 x D6 x D5 x D4 MSB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
Table 1.2.4 6-bitADPCM2 Algorithm
D7 x D6 x D5 MSB1 D4 5SB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
Table 1.2.5 7-bitADPCM2 Algorithm
D7 x D6 MSB1 D5 6SB1 D4 5SB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
Table 1.2.6 8-bit ADPCM2 Algorithm, 8-bit Non-linear PCM Algorithm, 8-bit straight PCM Algorithm
D7 MSB1 D6 7SB1 D5 6SB1 D4 5SB1 D3 4SB1 D2 3SB1 D1 2SB1 D0 LSB1
Table 1.2.7 16-bit straight PCM Algorithm
D7 MSB1 8SB1 D6 15SB1 7SB1 D5 14SB1 6SB1 D4 13SB1 5SB1 D3 12SB1 4SB1 D2 11SB1 3SB1 D1 10SB1 2SB1 D0 9SB1 LSB1
(first) (second)
x: Don't care
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FIFO Memory Configuration The ML2302 has two FIFO memories; one is for recording and other is for playback. The configuration of FIFO memory can be changed with a command. Select a FIFO configuration considering buffering times. Initially, FIFO memory for recording and FIFO memory for playback each is provided with 1024 bits (128 words x 8 bits). ML2302 cannot command recording and playback at the same time.
1. Combination of FIFO memory capacities Table 1.3.1 shows the combination of FIFO memory capacities in recording and playback modes.
Table 1.3.1
Mode Capacity 1024 bits 512 bits 256 bits Recording 128 w x 8 bits 64 w x 8 bits 32 w x 8 bits Playback 128 w x 8 bits 64 w x 8 bits 32 w x 8 bits *Initial value
2. Voice synthesis algorithms and maximum buffering times Table 1.3.2 shows the maximum buffering times when the FIFO capacity is 1024 bits and the sampling frequency is 8 kHz.
Table 1.3.2
Mode Voice synthesis algorithm 4-bit OKIADPCM 4-bit OKIADPCM2 5/6/7/8-bit OKIADPCM2 2-bit OKIADPCM2 8-bit straight PCM 16-bit straight PCM 8-bit OKI Non-linear PCM
Recording 32 ms 32 ms 16 ms 64 ms 16 ms 8 ms Note)
Playback 32 ms 32 ms 16 ms 64 ms 16 ms 8 ms 16 ms
Note: The 8-bit OKI Non-linear PCM algorithm cannot be used during recording.
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COMMAND LIST
Table 2.1
D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 D3 W3 X S3 C3 VH3 VL3 0 P3 R3 A3 0 F3 G3 I3 U3 Y3 D2 W2 X S2 C2 VH2 VL2 K2 P2 R2 A2 B2 F2 G2 0 U2 Y2 D1 0 X S1 C1 VH1 VL1 K1 P1 R1 A1 B1 F1 G1 J1 U1 Y1 D0 0 X S0 C0 VH0 VL0 K0 P0 0 0 B0 0 G0 J0 U0 Y0 Function POWER DOWN Disable Sets sampling frequency. RECORDING, PLAYBACK, STOP, PAUSE Volume control 1 Volume control 2 Level detection, noise injection Voice synthesis algorithm Analog specification 1 Analog specification 2 FIFO memory byte configuration Signal output format DMA Transfer Serial port Fast Forward/Rewind setting 1 (quick speaking/slow speaking) Fast Forward/Rewind setting 2
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READING STATUS
The ML2302 supports the following seven status flags. Table 4.1
Pin D7 D6 D5 D4 D3 D2 D1 D0 Status Data Recording/Playing flag Don't Care Pause flag Don't Care EMP Information Output flag MID Information flag FUL Information flag Data Transfer Error flag Description High when recording or playback is in progress High when playback of left voice is paused Output the same signal as the EMP pin. Note) Output the same signal as the MID pin. Note) Output the same signal as the FUL pin. Note) See "Data Transfer Errors".
Note:
EM, MID, and FUL are either at the active "H" or at the active "L" by setting the signal output format by the command. The status signals on D3 to D1 are determined depending on the status of the FIFOST pin as shown below.
D3 D2 D1
FIFOST = "0" EMP signal for playback FIFO MID signal for playback FIFO FUL signal for playback FIFO
FIFOST = "1" EMP signal for recording FIFO MID signal for recording FIFO FUL signal for recording FIFO
Data Transfer Errors The Data Transfer flag supports the following four errors. (1) "H" when data is read while EMP for recording FIFO is "H" (2) "H" when data is written while FUL for playback FIFO is "H" (3) "H" when a command is written while CBUSY is "L". (4) "H" when recording data cannot be written in FIFO while FUL for recording FIFO is "H". *These four errors are released when a normal transfer described below is carried out. (1) Reads data while EMP for recording FIFO is "L". (2) Writes data while FUL for playback FIFO is "L". (3) Writes a command while CBUSY is "H". (4) The error flag is released when data is written in recording FIFO within LSI after reading data from recording FIFO and setting FUL for recording FIFO to "L".
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ANALOG INPUT AMPLIFIER CIRCUIT
The ML2302 contains two OP amplifiers to amplify a voice signal from a microphone. Each OP amplifier is provided with the inverting input pin and output pin. The analog circuit reference voltage SG (signal ground) is input internally to the non-inverting input of each amplifier. For amplification, form an inverting amplifier circuit and adjust the amplification ratio by using external resistors.
C1 VLO 0.01 F 0.01 F R3 MOUT R4 VLOUT (Max) VLO MIN LIN LOUT 1/2VDD VLOUT (Min) GND OP amplifier 1 SG OP amplifier 2 VDD
Figure 6.1 The constants of R4 and C1 are determined by f = 1/2R*C. C1 is 39.89 pF 39 pF when R4 is 200 k, where the cut-off frequency of LPF is f = 20 kHz. During recording, the output VLO of the OP amplifier is input to LPF. Adjust the amplification ratio by an external resistor so that the output voltage VLOUT may be in the LOUT-permissible input voltage range. If VLOUT is not in this range, the waveform of the LPF output may be deformed. Table 6.1 shows an examples of LOUT-permissible input voltage ranges of the ML2302.
Table 6.1
Model name ML2302 Supply voltage VDD 3V LOUT-permissible voltage range VLOUT MIN 0.75 V MAX 2.25 V LOUT-permissible range 1.5 Vpp
The load resistance ROUTA of the OP amplifier is 50 k. Therefore, the feedback resistors R4 and R3 of the amplifying circuit must be 50 k or higher.
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SPEAKER DRIVING AMPLIFIER
The ML2302 contains two OP amplifiers for driving a speaker; SPOUT- which is the inverting type output for a voice multiplication signal SPIN and SPOUT+ which is the non-inverting type output. Though SPOUT+ alone can be used, when differential outputs are used, it is possible to gain not only an amplitude two times that of when a single OP amplifier is used but also a good volume even if a low power supply voltage is used. The connection diagram of differential outputs are shown below.
C1 AOUT R1 SPIN R2 SPOUT- SPOUT+ 20 k 20 k
VR
Note 1: The gain of a speaker amplifier is determined by R1 and R2.
V (SPOUT-) = -
R2 * V(SPIN) R1 R2 * V(SPIN) R1
V (SPOUT+) = -V(SPOUT-) =
Note 2: C1 is an AC coupling capacitance. The cut-off frequency at a low field is determined by the following equation. Select a value of C1 in accordance with a pass band.
1 2 x x C1 x R1
fc =
(Hz)
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RECORDING TIME AND MEMORY CAPACITY
The recording time of the ML2302 is dependent on the storage capacitance of external memory, the sampling frequency, and the width of ADPCM bits that have been specified. The recording time of the ML2302 is expressed by
Recording time = Memory size (in kbits) Sampling frequency (kHz) x Width of ADPCM bits x 4080 4096
For example, when 8.0 kHz of sampling frequency, 4 bits of ADPCM2, and 8 Mbits of memory size are set, the recording time is calculated below.
8000 4080 x 8.0 x 4 4096
Recording time =
= 249 seconds = 4 minutes 9 seconds
CONNECTION OF POWER SUPPLY
The ML2302 contains a single power supply as shown in Figure 7.1. The power supply is connected to the analog unit and digital unit separately.
DVDD ML2302 DGND
AVDD
AGND
Figure 7.1 Avoid following power supply connections.
Power supply for the analog circuit Power supply for the digital circuit DVDD DVDD AVDD
Power supply
DVDD
DVDD
AVDD
Figure 7.2
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APPLICATION CIRCUIT EXAMPLE
(1) MCU and External Interface
Memory
D7~0
ML2302 SPOUT SPOUTSPIN
MCU
DREQL DACKL IOW IOR RD WR CS D/C CH EMP MID FUL VOXO FIFOST SIOCK VCK DASD ADSD CBUSY BUSY RESET TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST9 TEST0 TEST8
AOUT MIN MOUT
LIN LOUT CB1 CB2 VR SPVDD SG
XT XT
DVDD DGND
AVDD AGND
AVDD(SP) AGND(SP)
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(2) Interface when DMA controller is Used
Memory
D7~0
ML2302 SPOUT SPOUT-
DMA
controller
DREQL DACKL IOW IOR
SPIN
AOUT MIN MOUT
MCU
RD WR CS D/C CH EMP MID FUL VOXO FIFOST SIOCK VCK DASD ADSD CBUSY BUSY RESET TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST9 TEST0 TEST8
LIN LOUT CB1 CB2 VR SPVDD SG
XT XT
DVDD DGND
AVDD AGND
AVDD(SP) AGND(SP)
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PACKAGE DIMENSIONS
(Unit: mm)
TQFP64-P-1010-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 0.26 TYP. 4/Oct. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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(Unit: mm)
P-VFLGA71-6.2x6.5-0.65-W
5
Notes for Mounting the Surface Mount Type Package
Package material Ball material Package weight (g) Rev. No./Last Revised
Epoxy resin Sn/Pb 0.03 TYP. 2/Oct. 31, 2000
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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REVISION HISTORY
Document No. FEDL2302DIGEST-01 FEDL2302DIGEST-02 FEDL2302DIGEST-03 Date Apr. 2001 Apr. 3, 2003 May 30, 2003 Page Previous Current Edition Edition - - - 1 FEDL2302DIGEST-04 Jan. 20, 2004 2 - 6 FEDL2302DIGEST-05 Dec. 27, 2004 19 19,20 Modified the application circuit example. - - - 1 2 10-18 6 Final edition 1 Final edition 2 Final edition 3 Partially changed contents "FEATURES" section. Modified the block diagram. Added pages. Partially corrected the Pin Descriptions. of the Description
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OKI Semiconductor
ML2302
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
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